HECC has deployed a testbed environment comprising a NEC SX-Aurora TSUBASA system hosting two nodes of NEC Vector Engines. To support current and future users who would like to evaluate the system for their needs, all NAS users are invited to a training session hosted by NEC on Tuesday, December 6, 2022 from 9:00 a.m. to 11:30 a.m. (Pacific Time).
Please see the abstract and agenda below, and keep an eye out for an email with login details for this online meeting.
NEC Vector Engine is a modern realization of a traditional vector architecture in its purest sense. While most modern architectures aim for high peak performance numbers through efficient cache utilization and core parallelization, the memory wall continues to persist—impacting the sustained performance of solvers with large datasets over long periods of simulation time. Vector processing targets high sustained performance by resolving the memory wall with higher memory performance through large memory bandwidths, however, it can be challenging to write good vectorized code that can leverage this memory performance.
This session has been designed to help HPC users understand the provisions and features of the NEC SDK, and how these features can be leveraged to write good vector code with basic knowledge of Fortran, C and C++ and no need for understanding any special programming frameworks.